From 456fe72cc5b026f9168af91767af6932f6e70866 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Wed, 25 Mar 2020 18:17:55 +0100 Subject: Finished up V2 of the PCB. --- PiCl/PiCl_master.sch | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'PiCl/PiCl_master.sch') diff --git a/PiCl/PiCl_master.sch b/PiCl/PiCl_master.sch index 3df7723..1a920e3 100644 --- a/PiCl/PiCl_master.sch +++ b/PiCl/PiCl_master.sch @@ -270,12 +270,6 @@ Wire Wire Line Connection ~ 7550 6150 Wire Wire Line 7550 6150 7550 6250 -Wire Wire Line - 8150 4550 7600 4550 -Wire Wire Line - 7600 4550 7600 5750 -Wire Wire Line - 7600 5750 7650 5750 Text GLabel 8750 3350 2 50 Output ~ 0 SCL Text GLabel 8750 3450 2 50 Output ~ 0 @@ -288,4 +282,5 @@ Text GLabel 7550 4950 0 50 Input ~ 0 SCL Text GLabel 7550 5050 0 50 Input ~ 0 SDA +NoConn ~ 7650 5750 $EndSCHEMATC -- cgit v1.2.3-70-g09d2