From eade5c17f6c84b37f1b622483ba5bfdfb0388133 Mon Sep 17 00:00:00 2001
From: Dennis Brentjes <d.brentjes@gmail.com>
Date: Tue, 24 Mar 2020 16:32:45 +0100
Subject: Finished routing a V1 pcb.

---
 PiCl/PiCl.pro | 52 +++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 37 insertions(+), 15 deletions(-)

(limited to 'PiCl/PiCl.pro')

diff --git a/PiCl/PiCl.pro b/PiCl/PiCl.pro
index 5d945d1..13942ce 100644
--- a/PiCl/PiCl.pro
+++ b/PiCl/PiCl.pro
@@ -1,4 +1,4 @@
-update=3/13/2020 16:32:00
+update=3/24/2020 11:22:50
 version=1
 last_client=kicad
 [general]
@@ -12,6 +12,16 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
 [pcbnew]
 version=1
 PageLayoutDescrFile=
@@ -237,9 +247,9 @@ dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
 [pcbnew/Netclasses/1]
-Name=PSU 5v
+Name=3a
 Clearance=0.2
-TrackWidth=8.09
+TrackWidth=1
 ViaDiameter=0.8
 ViaDrill=0.4
 uViaDiameter=0.3
@@ -248,9 +258,31 @@ dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
 [pcbnew/Netclasses/2]
-Name=RLY 5v
+Name=3aUSB
 Clearance=0.2
-TrackWidth=0.7
+TrackWidth=0.65
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/3]
+Name=FVCC
+Clearance=0.2
+TrackWidth=1.1
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
+[pcbnew/Netclasses/4]
+Name=VCC
+Clearance=0.2
+TrackWidth=1.1
 ViaDiameter=0.8
 ViaDrill=0.4
 uViaDiameter=0.3
@@ -258,13 +290,3 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-- 
cgit v1.2.3-70-g09d2